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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-30 13:51:13 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-30 13:51:13 -0800 |
| commit | 78b79dd1c983f510bb42ad34047e70c572ebf386 (patch) | |
| tree | 28382de365df4a50f8ca0dcd703bd42c05495b5d /src/machine.tex | |
| parent | c7793586787ed3c6f3d3cde0933341867a980d5d (diff) | |
| download | riscv-isa-manual-78b79dd1c983f510bb42ad34047e70c572ebf386.zip riscv-isa-manual-78b79dd1c983f510bb42ad34047e70c572ebf386.tar.gz riscv-isa-manual-78b79dd1c983f510bb42ad34047e70c572ebf386.tar.bz2 | |
Interrupts 16 and above are platform-defined
Platforms may avail them for custom use.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 55fdc1f..35f2c30 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1392,10 +1392,10 @@ interrupt-enable bits are hardwired to zero in the {\tt mip} and {\tt mie} registers respectively. Hence, these are all effectively \warl\ fields. -Implementations may add additional platform-specific machine-level -interrupt sources to bits 16 and above of the {\tt mip} and {\tt mie} -registers. The other unallocated interrupt sources (15--12, 10, 6, and 2) -are reserved for future standard use. +Implementations may add additional platform-specific interrupt sources to bits +16 and above of the {\tt mip} and {\tt mie} registers. Some platforms may +avail these interrupts for custom use. The other unallocated interrupt +sources (15--12, 10, 6, and 2) are reserved for future standard use. An interrupt {\em i} will be taken if bit {\em i} is set in both {\tt mip} and {\tt mie}, and if interrupts are globally enabled. By |