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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-21 01:54:40 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-21 01:54:40 -0800 |
| commit | 786d9b896c0b00b9665b28b39c0698ee7bde54bf (patch) | |
| tree | dd97d222703c72a74cb115beae9789bd833a380c /src/machine.tex | |
| parent | 19b4f2e67ad79266cc0072636abfd067a9d6667f (diff) | |
| download | riscv-isa-manual-786d9b896c0b00b9665b28b39c0698ee7bde54bf.zip riscv-isa-manual-786d9b896c0b00b9665b28b39c0698ee7bde54bf.tar.gz riscv-isa-manual-786d9b896c0b00b9665b28b39c0698ee7bde54bf.tar.bz2 | |
fix typos
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index c3edd9f..4fd6100 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1636,11 +1636,11 @@ circuitry. The counter-enable registers {\tt mcounteren} and {\tt scounteren} are 32-bit registers that -control the availability of the hardware performance monitoring +control the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. The settings in these registers only control accessibility. The act -of reading or writing these registers, does not affect the underlying +of reading or writing these registers does not affect the underlying counters, which continue to increment even when not accessible. When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} |