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authorAndrew Waterman <aswaterman@gmail.com>2018-11-30 14:01:53 -0800
committerGitHub <noreply@github.com>2018-11-30 14:01:53 -0800
commit71356274220e31b42d6b62dc4f6deaeeef9f42de (patch)
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Extend mstatus.TW to U-mode for M/U systems (#286)
Diffstat (limited to 'src/machine.tex')
-rw-r--r--src/machine.tex20
1 files changed, 14 insertions, 6 deletions
diff --git a/src/machine.tex b/src/machine.tex
index 35f2c30..e3d61bf 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -715,12 +715,14 @@ hooks necessary to lazily populate shadow page tables.
\end{commentary}
The TW (Timeout Wait) bit supports intercepting the WFI instruction (see
-Section~\ref{wfi}). When TW=0, the WFI instruction is permitted in S-mode.
-When TW=1, if WFI is executed in S-mode, and it does not complete within an
-implementation-specific, bounded time limit, the WFI instruction causes an
-illegal instruction trap. The time limit may always be 0, in which case WFI
-always causes an illegal instruction trap in S-mode when TW=1.
-TW is hard-wired to 0 when S-mode is not supported.
+Section~\ref{wfi}). When TW=0, the TW mechanism does not inhibit the WFI
+instruction from executing in the next-lowest privileged mode. When TW=1,
+then if WFI is executed in any less-privileged mode, and it does not complete
+within an implementation-specific, bounded time limit, the WFI instruction
+causes an illegal instruction exception. The time limit may always be 0, in which
+case WFI always causes an illegal instruction exception in less-privileged modes
+when TW=1. TW is hard-wired to 0 when there are no modes less privileged than
+M.
\begin{commentary}
Trapping the WFI
@@ -728,6 +730,12 @@ instruction can trigger a world switch to another guest OS, rather than
wastefully idling in the current guest.
\end{commentary}
+When S-mode is implemented, then executing WFI in U-mode causes an illegal
+instruction exception, unless it completes within an implementation-specific,
+bounded time limit. A future revision of this specification might add
+a feature that allows S-mode to selectively permit WFI in U-mode. Such
+a feature would only be active when TW=0.
+
The TSR (Trap SRET) bit supports intercepting the supervisor exception return
instruction, SRET. When TSR=1, attempts to execute SRET while executing in
S-mode will raise an illegal instruction exception. When TSR=0, this