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| author | Andrew Waterman <andrew@sifive.com> | 2018-05-02 14:03:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-02 14:03:21 -0700 |
| commit | 64786dec5330b6618fd0e0f63bd34bf399075beb (patch) | |
| tree | 598bb3889de670845161d2a8ff80cb35b75fca0d /src/machine.tex | |
| parent | de8d4a5b0d0957347f6ec88d02e8fe778b44f9f5 (diff) | |
| download | riscv-isa-manual-64786dec5330b6618fd0e0f63bd34bf399075beb.zip riscv-isa-manual-64786dec5330b6618fd0e0f63bd34bf399075beb.tar.gz riscv-isa-manual-64786dec5330b6618fd0e0f63bd34bf399075beb.tar.bz2 | |
Fix typo
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index cbc9445..c3dc2d2 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2075,7 +2075,7 @@ should now raise illegal instruction exceptions. The WFI instruction can also be executed when interrupts are disabled. The operation of WFI must be unaffected by the global interrupt bits in {\tt -mstatus} (MIE/SIE/UIE) and the delegation registers {\tt [m|s|u]ideleg} +mstatus} (MIE/SIE/UIE) and the delegation registers {\tt [m|s]ideleg} (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should |