Version of priv spec ready for ratification process

1 files changed, 11 insertions, 1 deletions

diff --git a/src/machine.tex b/src/machine.tex
index b130421..0bd5e0b 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1863,7 +1863,7 @@ The Interrupt bit in the {\tt mcause} register is set if the
 trap was caused by an interrupt. The Exception Code field
  contains a code identifying the last exception.  Table~\ref{mcauses}
 lists the possible machine-level exception codes.  The Exception Code
-is an \wlrl\ field, so is only guaranteed to hold supported exception
+is a \wlrl\ field, so is only guaranteed to hold supported exception
 codes.
 
 
@@ -2933,6 +2933,13 @@ Attempting to execute a store, store-conditional (regardless of success),
 or AMO instruction whose effective address lies within a PMP region without
 write permissions raises a store access exception.
 
+If MXLEN is changed, the contents of the {\tt pmp{\em x}cfg} fields are
+preserved, but appear in the {\tt pmpcfg{\em y}} CSR prescribed by the new
+setting of MXLEN.  For example, when MXLEN is changed from 64 to 32, {\tt
+pmp4cfg} moves from {\tt pmpcfg0}[39:32] to {\tt pmpcfg1}[7:0].  The {\tt
+pmpaddr} CSRs follow the usual CSR width modulation rules described in
+Section~\ref{sec:csrwidthmodulation}.
+
 \subsubsection*{Address Matching}
 
 The A field in a PMP entry's configuration register encodes the
@@ -3008,6 +3015,9 @@ If $G$ is the index of the least-significant bit set,
 the PMP granularity is $2^{G+2}$ bytes.
 \end{commentary}
 
+If the current XLEN is greater than MXLEN, the PMP address registers are
+zero-extended from MXLEN to XLEN bits for the purposes of address matching.
+
 \subsubsection*{Locking and Privilege Mode}
 
 The L bit indicates that the PMP entry is locked, i.e., writes to the