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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-11 07:43:12 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-07-11 07:43:12 -0700 |
| commit | 591ce7fdaccb0393667d9af1af30e956a505e104 (patch) | |
| tree | 78e9fc4551d435c41447abf469e99b4e4fa4217b /src/machine.tex | |
| parent | 4dc3fa254ccc54e6f090722810506602ea59dbce (diff) | |
| download | riscv-isa-manual-591ce7fdaccb0393667d9af1af30e956a505e104.zip riscv-isa-manual-591ce7fdaccb0393667d9af1af30e956a505e104.tar.gz riscv-isa-manual-591ce7fdaccb0393667d9af1af30e956a505e104.tar.bz2 | |
Clarify the behavior of M-mode hardware performance counters.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/src/machine.tex b/src/machine.tex index d8eeeb3..5829a57 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1488,18 +1488,21 @@ to the intermediate value of the comparand: \subsection{Hardware Performance Monitor} -M-mode includes a basic hardware performance monitoring facility. The {\tt -mcycle} CSR holds a count of the number of cycles the hart has executed since -some arbitrary time in the past. The {\tt minstret} CSR holds a count of the -number of instructions the hart has retired since some arbitrary time in the -past. The {\tt mcycle} and {\tt minstret} registers have 64-bit precision on -all RV32, RV64, and RV128 systems. +M-mode includes a basic hardware performance-monitoring facility. The +{\tt mcycle} CSR counts the number of cycles the hart has executed. +The {\tt minstret} CSR counts the number of instructions the hart has +retired. The {\tt mcycle} and {\tt minstret} registers have 64-bit +precision on all RV32, RV64, and RV128 systems. + +The counter registers have an arbitrary value after system reset, and +can be written with a given value. Any CSR write takes effect after +the writing instruction has otherwise completed. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt mhpmevent3}--{\tt mhpmevent31}, are MXLEN-bit \warl\ registers that control which event causes the corresponding counter to increment. The meaning of these events is -defined by the platform, but event 0 is reserved to mean ``no event.'' +defined by the platform, but event 0 is defined to mean ``no event.'' All counters should be implemented, but a legal implementation is to hard-wire both the counter and its corresponding event selector to 0. |