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authorJohn Hauser <31252952+jhauser-us@users.noreply.github.com>2020-08-25 13:51:33 -0700
committerGitHub <noreply@github.com>2020-08-25 13:51:33 -0700
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Change "hardwired to other field" to "read-only field" (#571)
Instead of describing CSR fields for XLEN (SXL, VSXL, UXL) and endianness (SBE, VSBE, UBE) as possibly being "hardwired" to another field, describe them as possibly being read-only fields with matching values.
Diffstat (limited to 'src/machine.tex')
-rw-r--r--src/machine.tex18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/machine.tex b/src/machine.tex
index 4c033cb..2f4cf7c 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -637,13 +637,13 @@ SXLEN=32 and UXLEN=32.
For RV64 systems, if S-mode is not supported, then SXL is hardwired
to zero. Otherwise, it is a \warl\ field that encodes the current value of
-SXLEN. In particular, the implementation may hardwire SXL so that
-SXLEN=MXLEN.
+SXLEN. In particular, an implementation may make SXL be a read-only
+field whose value always ensures that SXLEN=MXLEN.
For RV64 systems, if U-mode is not supported, then UXL is hardwired
to zero. Otherwise, it is a \warl\ field that encodes the current value of
-UXLEN. In particular, the implementation may hardwire UXL so that
-UXLEN=MXLEN or UXLEN=SXLEN.
+UXLEN. In particular, an implementation may make UXL be a read-only
+field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN.
Whenever XLEN in any mode is set to a value less than the widest
supported XLEN, all operations must ignore source operand register
@@ -664,7 +664,7 @@ case.
\end{commentary}
If MXLEN is changed from 32 to a wider width, each of {\tt mstatus} fields SXL and
-UXL, if not hardwired to a forced value, gets the value corresponding to the
+UXL, if not restricted to a single value, gets the value corresponding to the
widest supported width not wider than the new MXLEN.
\subsubsection{Memory Privilege in {\tt mstatus} Register}
@@ -751,10 +751,10 @@ In this case, no additional SFENCE.VMA is necessary, beyond what would
ordinarily be required for a world switch.
\end{commentary}
-If S-mode is supported, an implementation may hardwire SBE so that
-SBE=MBE and writes to SBE are ignored.
-If U-mode is supported, an implementation may hardwire UBE so that
-UBE=MBE or UBE=SBE and writes to UBE are ignored.
+If S-mode is supported, an implementation may make SBE be a read-only
+copy of MBE.
+If U-mode is supported, an implementation may make UBE be a read-only
+copy of either MBE or SBE.
\begin{commentary}
An implementation supports only little-endian memory accesses if fields