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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-26 01:08:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-26 01:12:49 -0700 |
| commit | 4abbead1038fa9366b177d289ebcf0b8da503617 (patch) | |
| tree | 6e46807a638a9880695749bf65d362bbd2590a9d /src/machine.tex | |
| parent | ca838c12b0bf61824e62eba60050a4dbc2604698 (diff) | |
| download | riscv-isa-manual-4abbead1038fa9366b177d289ebcf0b8da503617.zip riscv-isa-manual-4abbead1038fa9366b177d289ebcf0b8da503617.tar.gz riscv-isa-manual-4abbead1038fa9366b177d289ebcf0b8da503617.tar.bz2 | |
Custom interrupt priorities are custom
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 438f75a..e44c0af 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1388,13 +1388,13 @@ Synchronous exceptions are of lower priority than all interrupts. The machine-level interrupt fixed-priority ordering rules were developed with the following rationale. - The platform-specific machine-level interrupt sources in bits 16 and - above have the highest service priority to support very fast local - vectored interrupts. - Interrupts for higher privilege modes must be serviced before interrupts for lower privilege modes to support pre-emption. + The platform-specific machine-level interrupt sources in bits 16 and above + have platform-specific priority, but are typically chosen to have the + highest service priority to support very fast local vectored interrupts. + External interrupts are handled before internal (timer/software) interrupts as external interrupts are usually generated by devices that might require low interrupt service times. |