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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-12 17:47:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-12 17:47:16 -0700 |
| commit | 48df4e3688823c01dbca5e61b2f2e8cfb6ebd6d9 (patch) | |
| tree | 0bfc2c52e9d6b0793f174b824389427669f45b27 /src/machine.tex | |
| parent | c643f44e6ec8026530ce808f4d26851f4badfda3 (diff) | |
| download | riscv-isa-manual-48df4e3688823c01dbca5e61b2f2e8cfb6ebd6d9.zip riscv-isa-manual-48df4e3688823c01dbca5e61b2f2e8cfb6ebd6d9.tar.gz riscv-isa-manual-48df4e3688823c01dbca5e61b2f2e8cfb6ebd6d9.tar.bz2 | |
Fix typo
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 55ef739..4d43bae 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2049,7 +2049,7 @@ instruction per privilege level. If the A extension is supported, the {\em x},RET instruction is allowed to clear any outstanding LR address reservation but is not -required to. Trap handlers should explicity clear the reservation if +required to. Trap handlers should explicitly clear the reservation if required (e.g., by using a dummy SC) before executing the {\em x}RET. \begin{commentary} |