Clarify that mtval/mepc are set on interrupts, too

1 files changed, 4 insertions, 4 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 024daca..9189a81 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1729,8 +1729,8 @@ addresses.  Implementations may convert some invalid address patterns into
 other invalid addresses prior to writing them to {\tt mepc}.
 
 When a trap is taken into M-mode, {\tt mepc} is written with the virtual
-address of the instruction that encountered the exception.  Otherwise,
-{\tt mepc} is never written by the implementation, though it may be
+address of the instruction that encountered the exception or was interrupted.
+Otherwise, {\tt mepc} is never written by the implementation, though it may be
 explicitly written by software.
 
 \begin{figure}[h!]
@@ -1860,9 +1860,9 @@ When a hardware breakpoint is triggered, or an instruction-fetch, load, or
 store address-misaligned, access, or page-fault exception occurs, {\tt
   mtval} is written with the faulting virtual address.  On an illegal
 instruction trap, {\tt mtval} may be written with the first XLEN or ILEN
-bits of the faulting instruction as described below.  For other exceptions,
+bits of the faulting instruction as described below.  For other traps,
 {\tt mtval} is set to zero, but a future standard may redefine {\tt
-  mtval}'s setting for other exceptions.
+  mtval}'s setting for other traps.
 
 \begin{commentary}
   The {\tt mtval} register replaces the {\tt mbadaddr} register in