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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-26 17:04:57 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-26 17:04:57 -0700 |
| commit | 3be673153b19d4cb9756344f62929ce32c2a1d24 (patch) | |
| tree | 3cc2f016a693a388275c68957eb7b056272452eb /src/machine.tex | |
| parent | cac9ad6fedf57a0cff22caa5e9b8252a7290cb5d (diff) | |
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Clarified that counter-enable fields don't change underlying counter values.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 4d43bae..024daca 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1624,6 +1624,12 @@ are 32-bit registers that control the availability of the hardware performance monitoring counters to the next-lowest privileged mode. +The settings in these registers only control accessibility. The act +of reading or writing these registers, does not affect the underlying +counters, except for the expected side effects of any instruction +execution (i.e., {\tt instret} will be incremented after a write to +these CSRs). + When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} register is clear, attempts to read the {\tt cycle}, {\tt time}, {\tt instret}, or {\tt hpmcounter{\em n}} register while executing in |