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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:40:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-06 19:40:05 -0800 |
| commit | 399c74ab450e9ce34944a1a8e06de93b250efd84 (patch) | |
| tree | 62564dddb26061262e0ad17cca3e05b495edb5f4 /src/machine.tex | |
| parent | e2c243a3b1056fbd8b34b8b222a0467f405c0e21 (diff) | |
| download | riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.zip riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.tar.gz riscv-isa-manual-399c74ab450e9ce34944a1a8e06de93b250efd84.tar.bz2 | |
spelling20181106-Base-Ratification
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 0341cc7..6de2495 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1396,7 +1396,7 @@ Synchronous exceptions are of lower priority than all interrupts. with the following rationale. Interrupts for higher privilege modes must be serviced before - interrupts for lower privilege modes to support pre-emption. + interrupts for lower privilege modes to support preemption. The platform-specific machine-level interrupt sources in bits 16 and above have platform-specific priority, but are typically chosen to have the |