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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-09 11:00:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-09 11:00:58 -0800 |
| commit | 14e18f2036c82943e52ca8bf630fd8e4f53b7e4a (patch) | |
| tree | b93f377af0c6947b9cfb5088dcfb037f3dc4ffcc /src/machine.tex | |
| parent | 7cf3673198998d38b7235c879974cdcfa0912031 (diff) | |
| download | riscv-isa-manual-14e18f2036c82943e52ca8bf630fd8e4f53b7e4a.zip riscv-isa-manual-14e18f2036c82943e52ca8bf630fd8e4f53b7e4a.tar.gz riscv-isa-manual-14e18f2036c82943e52ca8bf630fd8e4f53b7e4a.tar.bz2 | |
fix typos
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index b2e753b..fe4756f 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1267,7 +1267,7 @@ The SEIP field in {\tt mip} contains a single read-write bit. SEIP may be written by M-mode software to indicate to S-mode that an external interrupt is pending. Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts. The -logical-OR of the software-writeable bit and the signal from the +logical-OR of the software-writable bit and the signal from the external interrupt controller is used to generate external interrupts to the supervisor. When the SEIP bit is read with a CSRRW, CSRRS, or CSRRC instruction, the value returned in the {\tt rd} destination |