Don't reference the SBI in normative privileged spec sections

Submitted on behalf of Christoph Hellwig

For context, see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/kL-2LhgUmcE/xxySlYT0CQAJ

1 files changed, 6 insertions, 14 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 747c97a..18aeedf 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -968,14 +968,6 @@ restored using standard instructions (F, D, and/or Q), and privileged
 code must be aware of FLEN to determine the appropriate space to
 reserve for each {\tt f} register.
 
-In a supervisor-level OS, any additional user-mode state should be
-initialized, saved, and restored using SBI calls that treats the
-additional context as an opaque object of a fixed maximum size.  The
-implementation of the SBI initialize, save, and restore calls might
-require additional implementation-dependent privileged instructions to
-initialize, save, and restore microarchitectural state inside a
-coprocessor.
-
 All privileged modes share a single copy of the FS and XS bits.  In a
 system with more than one privileged mode, supervisor mode would
 normally use the FS and XS bits directly to record the status with
@@ -1327,11 +1319,11 @@ from code running on the local hart at the associated or any higher
 privilege level. The machine-level MSIP bits are written by accesses
 to memory-mapped control registers, which are used by remote harts to
 provide machine-mode interprocessor interrupts.  Interprocessor
-interrupts for lower privilege levels are implemented through ABI and
-SBI calls to the AEE or SEE respectively, which might ultimately
-result in a machine-mode write to the receiving hart's MSIP bit.  A
-hart can write its own MSIP bit using the same memory-mapped control
-register.
+interrupts for lower privilege levels are implemented through
+implementation-specific mechanisms, e.g., via calls to an AEE or SEE,
+which might ultimately result in
+a machine-mode write to the receiving hart's MSIP bit.  A hart can write its
+own MSIP bit using the same memory-mapped control register.
 
 The MSIE, SSIE, and USIE fields in the {\tt mie} CSR enable M-mode software
 interrupts, S-mode software interrupts, and U-mode software interrupts,
@@ -1341,7 +1333,7 @@ respectively.
 We only allow a hart to directly write its own SSIP or USIP
 bits when running in the appropriate mode, as other harts might be
 virtualized and possibly descheduled by higher privilege levels.  We
-rely on ABI and SBI calls to provide interprocessor interrupts
+rely on calls to the AEE and SEE to provide interprocessor interrupts
 for this reason.  Machine-mode harts are not virtualized and can
 directly interrupt other harts by setting their MSIP bits, typically
 using uncached I/O writes to memory-mapped control registers depending