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| author | Alexandre Joannou <gameboo@users.noreply.github.com> | 2018-05-30 17:45:24 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-30 09:45:24 -0700 |
| commit | 6f2b2a81da124bccf5c072dd2e99bf54a4eea121 (patch) | |
| tree | ace0f25789eb59323c23b2f688a0842fa8fb49ef /src/m.tex | |
| parent | 4a29140ef57e38532b3d3e43c9cd49e07066e7e0 (diff) | |
| download | riscv-isa-manual-6f2b2a81da124bccf5c072dd2e99bf54a4eea121.zip riscv-isa-manual-6f2b2a81da124bccf5c072dd2e99bf54a4eea121.tar.gz riscv-isa-manual-6f2b2a81da124bccf5c072dd2e99bf54a4eea121.tar.bz2 | |
Disambiguate division operands (#179)
Diffstat (limited to 'src/m.tex')
| -rw-r--r-- | src/m.tex | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -90,8 +90,8 @@ MULDIV & divisor & dividend & DIV[U]W/REM[U]W & dest & OP-32 \\ \end{tabular} \end{center} -DIV and DIVU perform signed and unsigned integer division of XLEN -bits by XLEN bits, rounding towards zero. +DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer +division of {\em rs1} by {\em rs2}, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation. If both the quotient and remainder are required from the same division, the recommended code sequence is: |