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author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-04-02 14:58:44 -0700 |
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committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-04-02 14:58:44 -0700 |
commit | 878d4d3fde24aea2958cebe08894bf4e4a2e04d0 (patch) | |
tree | b5e3af50fd959827d152f62908c48bc99f347c92 /src/m.tex | |
parent | d8b75c803428c9d4364fa456c9347bd7215067bf (diff) | |
download | riscv-isa-manual-878d4d3fde24aea2958cebe08894bf4e4a2e04d0.zip riscv-isa-manual-878d4d3fde24aea2958cebe08894bf4e4a2e04d0.tar.gz riscv-isa-manual-878d4d3fde24aea2958cebe08894bf4e4a2e04d0.tar.bz2 |
Added rationale for choice of divide overflow results.
Diffstat (limited to 'src/m.tex')
-rw-r--r-- | src/m.tex | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -136,4 +136,12 @@ branch instruction needs to be added to each divide operation, and this branch instruction can be inserted after the divide and should normally be very predictably not taken, adding little runtime overhead. + +The value of all bits set is returned for both unsigned and signed +divide by zero to simplify the divider circuitry. The value of all 1s +is both the natural value to return for unsigned divide, representing +the largest unsigned number, and also the natural result for simple +unsigned divider implementations. Signed division is often +implemented using an unsigned division circuit and specifying the same +overflow result simplifies the hardware. \end{commentary} |