Big-endian or bi-endian memory systems should not

be considered non-standard, but could be future standard variants.

1 files changed, 7 insertions, 7 deletions

diff --git a/src/intro.tex b/src/intro.tex
index 22a57c3..2896e9d 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -470,13 +470,13 @@ fault when such an instruction borders a protection boundary,
 complicating variable-instruction-length fetch and decode.
 \end{commentary}
 
-The base RISC-V ISA has a little-endian memory system, but
-non-standard variants can provide a big-endian or bi-endian memory
+Current RISC-V base ISAs have little-endian memory systems, but
+future variants might provide a big-endian or bi-endian memory
 system.  Instructions are stored in memory with each 16-bit parcel
 stored in a memory halfword according to the implementation's natural
 endianness. Parcels forming one instruction are stored at
-increasing halfword addresses, with the lowest addressed parcel
-holding the lowest numbered bits in the instruction specification,
+increasing halfword addresses, with the lowest-addressed parcel
+holding the lowest-numbered bits in the instruction specification,
 i.e., instructions are always stored in a little-endian sequence of
 parcels regardless of the memory system endianness.  The code sequence
 in Figure~\ref{fig:storeinstruction} will store a 32-bit instruction
@@ -503,16 +503,16 @@ x86 systems; iOS, Android, and Windows for ARM).  A minor point is
 that we have also found little-endian memory systems to be more
 natural for hardware designers.  However, certain application areas,
 such as IP networking, operate on big-endian data structures, and so
-we leave open the possibility of non-standard big-endian or bi-endian
+we leave open the possibility of future big-endian or bi-endian
 systems.
 
 We have to fix the order in which instruction parcels are stored in
 memory, independent of memory system endianness, to ensure that the
 length-encoding bits always appear first in halfword address
 order. This allows the length of a variable-length instruction to be
-quickly determined by an instruction fetch unit by examining only the
+quickly determined by an instruction-fetch unit by examining only the
 first few bits of the first 16-bit instruction parcel.  Once we had
-decided to fix on a little-endian memory system and instruction parcel
+decided to fix on a native little-endian memory system and instruction parcel
 ordering, this naturally led to placing the length-encoding bits in
 the LSB positions of the instruction format to avoid breaking up
 opcode fields.