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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-21 15:10:48 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-21 15:10:48 -0800 |
| commit | 9674e5a7ea75291071aeab086c260e133cf8e31d (patch) | |
| tree | b4f958a49d0e673520b8ef0a7cbabccd31ca83cd /src/intro.tex | |
| parent | b78fd79cf2df7390162a4e77af772aa77bd8d740 (diff) | |
| download | riscv-isa-manual-9674e5a7ea75291071aeab086c260e133cf8e31d.zip riscv-isa-manual-9674e5a7ea75291071aeab086c260e133cf8e31d.tar.gz riscv-isa-manual-9674e5a7ea75291071aeab086c260e133cf8e31d.tar.bz2 | |
Address space is circular
Closes #40
Diffstat (limited to 'src/intro.tex')
| -rw-r--r-- | src/intro.tex | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/intro.tex b/src/intro.tex index b95c6b3..2629f6e 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -344,12 +344,18 @@ regardless of any subsequent extensions. \section{Memory} -A RISC-V hart has a single byte-addressable address space for all memory +A RISC-V hart has a single byte-addressable address space +of $2^{XLEN}$ bytes for all memory accesses. A {\em word} of memory is defined as \wunits{32}{bits} (\wunits{4}{bytes}). Correspondingly, a {\em halfword} is \wunits{16}{bits} (\wunits{2}{bytes}), a {\em doubleword} is \wunits{64}{bits} (\wunits{8}{bytes}), and a {\em quadword} is \wunits{128}{bits} (\wunits{16}{bytes}). +The memory address space is circular, so that the byte at address +$2^{XLEN}-1$ is adjacent to the byte at address zero. Accordingly, memory +address computations done by the hardware ignore overflow and instead +wrap around modulo $2^{XLEN}$. + The execution environment determines the mapping of hardware resources into a hart's address space. |