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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-07 23:46:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-07 23:46:35 -0700 |
| commit | 3536b679c4fcfb2cf833302d1bf960864b4c4a66 (patch) | |
| tree | 0c276ceca5fb9f540ced27cdc63601e43735721d /src/intro.tex | |
| parent | ce5e74a66ea22327702eca09e7a868db7e9615e9 (diff) | |
| download | riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.zip riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.tar.gz riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.tar.bz2 | |
Use \geq instead of >=
Diffstat (limited to 'src/intro.tex')
| -rw-r--r-- | src/intro.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intro.tex b/src/intro.tex index a5fd3bd..e17722a 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -459,7 +459,7 @@ word. As described in Chapter~\ref{extensions}, an implementation that does not require support for the standard compressed instruction extension can map 3 additional non-conforming 30-bit instruction spaces into the 32-bit fixed-width format, while preserving support -for standard $>=$32-bit instruction-set extensions. Further, if the +for standard $\geq$32-bit instruction-set extensions. Further, if the implementation also does not need instructions $>$32-bits in length, it can recover a further four major opcodes for non-conforming extensions. \end{samepage-commentary} |