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| author | Andrew Waterman <andrew@sifive.com> | 2017-12-06 16:49:00 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-12-06 16:49:00 -0800 |
| commit | 8aa58b50600aea8091a3357e1c89e5894e228465 (patch) | |
| tree | 5cd1f2fe79060b0f20c3d1ddb0e35499c9fc58b9 /src/intro.tex | |
| parent | b62e649445d1f02dfcc8123f64dce598baceb5ab (diff) | |
| download | riscv-isa-manual-8aa58b50600aea8091a3357e1c89e5894e228465.zip riscv-isa-manual-8aa58b50600aea8091a3357e1c89e5894e228465.tar.gz riscv-isa-manual-8aa58b50600aea8091a3357e1c89e5894e228465.tar.bz2 | |
Make explicit that 0xFFFF is an illegal opcode
Diffstat (limited to 'src/intro.tex')
| -rw-r--r-- | src/intro.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intro.tex b/src/intro.tex index c1d8023..5d7b2f1 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -344,7 +344,8 @@ Instruction lengths between 80 bits and 176 bits are encoded using a 3-bit field in bits [14:12] giving the number of 16-bit words in addition to the first 5$\times$16-bit words. The encoding with bits [14:12] set to {\tt 111} is reserved for future longer instruction -encodings. +encodings. The encodings with bits [15:0] all zeros or all ones are +illegal. \begin{figure}[hbt] { |