Add Hauser's definition of "memory access"

1 files changed, 55 insertions, 0 deletions

diff --git a/src/intro.tex b/src/intro.tex
index 4d29ef2..05aa5ea 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -344,6 +344,61 @@ new instructions as further optional extensions.  For example, the
 base integer ISAs will continue as fully supported standalone ISAs,
 regardless of any subsequent extensions.
 
+\section{Memory}
+
+Executing each RISC-V machine instruction entails one or more {\em memory
+accesses}.  A RISC-V platform has a single byte-addressable address space for
+all memory accesses.  A {\em word} is defined as \wunits{32}{bits}
+(\wunits{4}{bytes}).  Correspondingly, a {\em halfword} is \wunits{16}{bits}
+(\wunits{2}{bytes}), a {\em doubleword} is \wunits{64}{bits}
+(\wunits{8}{bytes}), and a {\em quadword} is \wunits{128}{bits}
+(\wunits{16}{bytes}).
+
+The memory accesses made by RISC-V instructions are subdivided into {\em
+implicit} and {\em explicit} accesses.  For each instruction executed, an {\em
+implicit} memory read (instruction fetch) is done to obtain the encoded
+instruction to execute.  Many RISC-V instructions perform no further memory
+accesses beyond instruction fetch.  Specific load and store instructions
+perform an {\em explicit} read or write of memory at an address determined by
+the instruction.  The execution environment may dictate that instruction
+execution performs other {\em implicit} memory accesses (such as to implement
+address translation) beyond those documented for the unprivileged ISA.
+
+The execution environment determines what portions of the address space are
+accessible for each kind of memory access.  For example, the set of locations
+that can be implicitly read for instruction fetch may or may not have any
+overlap with the set of locations that can be explicitly read by a load
+instruction; and the set of locations that can be explicitly written by
+a store instruction may be only a subset of locations that can be read.
+Ordinarily, if an instruction attempts to access memory at an inaccessible
+address, an exception is raised for the instruction.
+
+Except when specified otherwise, implicit reads that do not raise an exception
+may occur arbitrarily early and speculatively, even before the machine could
+possibly prove that the read will be needed.  For instance, a valid
+implementation could attempt to read all of memory at the earliest
+opportunity, cache as many fetchable (executable) bytes as possible for later
+instruction fetches, and avoid reading memory for instruction fetches ever
+again.  To ensure that certain implicit reads are ordered only after writes to
+the same memory locations, software must execute specific fence or cache
+control instructions defined for this purpose (such as the FENCE.I instruction
+defined in Chapter~\ref{chap:zifencei}).
+
+The memory accesses (implicit or explicit) made by a hart may appear to occur
+in a different order as perceived by another hart or by any other agent that
+can access the same memory.  This perceived reordering of memory accesses is
+always constrained, however, by the applicable memory consistency model.  The
+default memory consistency model for RISC-V is the RISC-V Weak Memory Ordering
+(RVWMO), defined in Chapter~\ref{ch:memorymodel} and in appendices.
+Optionally, an implementation may adopt the stronger model of Total Store
+Ordering, as defined in Chapter~\ref{sec:ztso}.  The execution environment may
+also add constraints that further limit the perceived reordering of memory
+accesses.  Software that assumes only the RVWMO model is compatible with the
+actual memory consistency rules of all RISC-V implementations.  As with
+implicit reads, software must execute fence or cache control instructions to
+ensure specific ordering of memory accesses beyond the requirements of the
+assumed memory consistency model and execution environment.
+
 \section{Instruction Length Encoding}
 
 The base RISC-V ISA has fixed-length 32-bit instructions that must be