diff options
| author | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:25:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:26:42 -0700 |
| commit | 40cf9350a6bf1c47d21a91fcdd1ba62a28731303 (patch) | |
| tree | 14484d7243dd344af851687d7fa9cd642b19ab54 /src/intro.tex | |
| parent | d01dabf2c290dae77d12c8cfa288e6f9ac95cb55 (diff) | |
| download | riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.zip riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.gz riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.bz2 | |
Hyphenate "instruction set" when it's part of a noun phrase
Diffstat (limited to 'src/intro.tex')
| -rw-r--r-- | src/intro.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intro.tex b/src/intro.tex index d9e1f57..884c30b 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -1,6 +1,6 @@ \chapter{Introduction} -RISC-V (pronounced ``risk-five'') is a new instruction set +RISC-V (pronounced ``risk-five'') is a new instruction-set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry @@ -83,7 +83,7 @@ instruction fetch unit. A RISC-V-compatible core might support multiple RISC-V-compatible hardware threads, or {\em harts}, through multithreading. -A RISC-V core might have additional specialized instruction set +A RISC-V core might have additional specialized instruction-set extensions or an added {\em coprocessor}. We use the term {\em coprocessor} to refer to a unit that is attached to a RISC-V core and is mostly sequenced by a RISC-V instruction stream, but which |