48+-bit instruction-length encoding scheme is not frozen

See issue #280

1 files changed, 19 insertions, 11 deletions

diff --git a/src/intro.tex b/src/intro.tex
index 05977ac..be87c73 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -427,7 +427,7 @@ implicit reads, software must execute fence or cache-control instructions to
 ensure specific ordering of memory accesses beyond the requirements of the
 assumed memory consistency model and execution environment.
 
-\section{Instruction Length Encoding}
+\section{Base Instruction-Length Encoding}
 
 The base RISC-V ISA has fixed-length 32-bit instructions that must be
 naturally aligned on 32-bit boundaries.  However, the standard RISC-V
@@ -456,15 +456,23 @@ Figure~\ref{instlengthcode} illustrates the standard RISC-V
 instruction-length encoding convention.  All the 32-bit instructions
 in the base ISA have their lowest two bits set to {\tt 11}.  The
 optional compressed 16-bit instruction-set extensions have their
-lowest two bits equal to {\tt 00}, {\tt 01}, or {\tt 10}.  Standard
-instruction-set extensions encoded with more than 32 bits have
-additional low-order bits set to {\tt 1}, with the conventions for
-48-bit and 64-bit lengths shown in Figure~\ref{instlengthcode}.
-Instruction lengths between 80 bits and 176 bits are encoded using a
-3-bit field in bits [14:12] giving the number of 16-bit words in
-addition to the first 5$\times$16-bit words.  The encoding with bits
-[14:12] set to {\tt 111} is reserved for future longer instruction
-encodings.
+lowest two bits equal to {\tt 00}, {\tt 01}, or {\tt 10}.
+
+\subsection*{Expanded Instruction-Length Encoding}
+
+A portion of the 32-bit instruction-encoding space has been allocated for
+instructions longer than 32 bits.  The entirety of this space is reserved at
+this time, and the following proposal for encoding instructions longer
+than 32 bits is not considered frozen.
+
+Standard instruction-set extensions
+encoded with more than 32 bits have additional low-order bits set to {\tt 1},
+with the conventions for 48-bit and 64-bit lengths shown in
+Figure~\ref{instlengthcode}.  Instruction lengths between 80 bits and 176 bits
+are encoded using a 3-bit field in bits [14:12] giving the number of 16-bit
+words in addition to the first 5$\times$16-bit words.  The encoding with bits
+[14:12] set to {\tt 111} is reserved for future longer instruction encodings.
+
 
 \begin{figure}[hbt]
 {
@@ -514,7 +522,7 @@ Byte Address: & \multicolumn{1}{r}{base+4} & \multicolumn{1}{r}{base+2} & \multi
  \end{tabular}
 \end{center}
 }
-\caption{RISC-V instruction length encoding.}
+\caption{RISC-V instruction length encoding.  Only the 16-bit and 32-bit encodings are considered frozen at this time.}
 \label{instlengthcode}
 \end{figure}