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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-30 14:58:28 -0800 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-30 14:58:28 -0800 |
| commit | 0dc31ffdd84bfb04214a5e78e3208ecc664ef403 (patch) | |
| tree | 18c055b603dc1d287ce0bc888d7ae4058c7d5cf6 /src/intro.tex | |
| parent | 1d8fbc86a56d9b200bdc6fa5d20afa2aa0d3af8d (diff) | |
| download | riscv-isa-manual-0dc31ffdd84bfb04214a5e78e3208ecc664ef403.zip riscv-isa-manual-0dc31ffdd84bfb04214a5e78e3208ecc664ef403.tar.gz riscv-isa-manual-0dc31ffdd84bfb04214a5e78e3208ecc664ef403.tar.bz2 | |
Be more tentative
Diffstat (limited to 'src/intro.tex')
| -rw-r--r-- | src/intro.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/intro.tex b/src/intro.tex index be87c73..7448425 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -460,10 +460,10 @@ lowest two bits equal to {\tt 00}, {\tt 01}, or {\tt 10}. \subsection*{Expanded Instruction-Length Encoding} -A portion of the 32-bit instruction-encoding space has been allocated for -instructions longer than 32 bits. The entirety of this space is reserved at -this time, and the following proposal for encoding instructions longer -than 32 bits is not considered frozen. +A portion of the 32-bit instruction-encoding space has been tentatively +allocated for instructions longer than 32 bits. The entirety of this space is +reserved at this time, and the following proposal for encoding instructions +longer than 32 bits is not considered frozen. Standard instruction-set extensions encoded with more than 32 bits have additional low-order bits set to {\tt 1}, |