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| author | Bill Traynor <wmat@riscv.org> | 2022-12-15 11:36:32 -0800 |
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| committer | Bill Traynor <wmat@riscv.org> | 2022-12-15 11:36:32 -0800 |
| commit | d2f9d97b3d665c48e3abdd85782e5337a5496936 (patch) | |
| tree | 4b6880de3500ea5cdeba6f3e6cd2a1815fe75871 /src/intro.adoc | |
| parent | 5fd81813a6f5fd7ed07d1ebb069f26d70836365d (diff) | |
| download | riscv-isa-manual-d2f9d97b3d665c48e3abdd85782e5337a5496936.zip riscv-isa-manual-d2f9d97b3d665c48e3abdd85782e5337a5496936.tar.gz riscv-isa-manual-d2f9d97b3d665c48e3abdd85782e5337a5496936.tar.bz2 | |
Changed another "W" to *W to match LaTeX.
Changed another "W" to *W to match LaTeX.
Diffstat (limited to 'src/intro.adoc')
| -rw-r--r-- | src/intro.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index b8aba29..94d6a67 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -279,7 +279,7 @@ RISC-V design was changed to the current choice in January 2011. Our focus was on supporting 32-bit integers in the 64-bit ISA not on providing compatibility with the 32-bit ISA, and the motivation was to remove the asymmetry that arose from having not all opcodes in RV32I -have a "W" suffix (e.g., ADDW, but AND not ANDW). In hindsight, this was +have a *W suffix (e.g., ADDW, but AND not ANDW). In hindsight, this was perhaps not well-justified and a consequence of designing both ISAs at the same time as opposed to adding one later to sit on top of another, and also from a belief we had to fold platform requirements into the ISA |