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authorkanataso <kanapo.go@gmail.com>2023-07-12 23:25:35 +0900
committerAndrew Waterman <andrew@sifive.com>2023-07-12 13:40:16 -0700
commit8631b79db26cb338cb2b697e5afeb1350396df51 (patch)
tree86fb14560bc1f749ac5eef4f9c051561101562d6 /src/intro.adoc
parent88f0547851943bdfd2f20ce29528b7030afee360 (diff)
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Add RV64E to Base Integer ISA
RV32E and RV64E Base Integer Instruction Sets is Ratified. Signed-off-by: kanataso <kanapo.go@gmail.com>
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@@ -221,9 +221,9 @@ integer variants, RV32I and RV64I, described in
<<rv32>> and <<rv64>>, which provide 32-bit
or 64-bit address spaces respectively. We use the term XLEN to refer to
the width of an integer register in bits (either 32 or 64).
-<<rv32e, Chapter 6>> describes the RV32E subset variant of the
-RV32I base instruction set, which has been added to support small
-microcontrollers, and which has half the number of integer registers.
+<<rv32e, Chapter 6>> describes the RV32E and RV64E subset variants of the
+RV32I or RV64I base instruction sets respectively, which have been added to support small
+microcontrollers, and which have half the number of integer registers.
<<rv128, Chapter 8>> sketches a future RV128I variant of the
base integer instruction set supporting a flat 128-bit address space
(XLEN=128). The base integer instruction sets use a two's-complement