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| author | Andrew Waterman <andrew@sifive.com> | 2023-09-19 17:13:47 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-19 17:13:47 -0700 |
| commit | 45cddfbe9866ce65b02190ac1ea975bd1259c8b3 (patch) | |
| tree | bbd8e9e0594bc27efd1b3ae817cf052baf1d1699 /src/intro.adoc | |
| parent | 5a7c70df3718f8babaa06347acaf19b628f2988b (diff) | |
| download | riscv-isa-manual-45cddfbe9866ce65b02190ac1ea975bd1259c8b3.zip riscv-isa-manual-45cddfbe9866ce65b02190ac1ea975bd1259c8b3.tar.gz riscv-isa-manual-45cddfbe9866ce65b02190ac1ea975bd1259c8b3.tar.bz2 | |
Hyphenate "virtual-/illegal-instruction exception" (#1133)
Diffstat (limited to 'src/intro.adoc')
| -rw-r--r-- | src/intro.adoc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index 8936b91..f18a26e 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -258,8 +258,8 @@ reserved for instructions only required by wider address-space variants. The main disadvantage of not treating the design as a single ISA is that it complicates the hardware needed to emulate one base ISA on another -(e.g., RV32I on RV64I). However, differences in addressing and illegal -instruction traps generally mean some mode switch would be required in +(e.g., RV32I on RV64I). However, differences in addressing and +illegal-instruction traps generally mean some mode switch would be required in hardware in any case even with full superset instruction encodings, and the different RISC-V base ISAs are similar enough that supporting multiple versions is relatively low cost. Although some have proposed @@ -531,7 +531,7 @@ An implementation of the standard IMAFD ISA need only hold the most-significant 30 bits in instruction caches (a 6.25% saving). On instruction cache refills, any instructions encountered with either low bit clear should be recoded into illegal 30-bit instructions before -storing in the cache to preserve illegal instruction exception behavior. +storing in the cache to preserve illegal-instruction exception behavior. Perhaps more importantly, by condensing our base ISA into a subset of the 32-bit instruction word, we leave more space available for @@ -572,7 +572,7 @@ standard binary library used by many different machines). Defining a 32-bit word of all ones as illegal was also considered, as all machines must support a 32-bit instruction size, but this requires the instruction-fetch unit on machines with ILEN >32 report an -illegal instruction exception rather than an access-fault exception when +illegal-instruction exception rather than an access-fault exception when such an instruction borders a protection boundary, complicating variable-instruction-length fetch and decode. ==== |