diff options
| author | Bill Traynor <wmat@riscv.org> | 2022-12-17 10:34:15 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-12-17 10:34:15 -0500 |
| commit | 1078de3a8e6ffd01a6ea8e6f19950dc6309b4ca8 (patch) | |
| tree | 60f9e25e51d1619c111e2798c3f5b523977c56b0 /src/intro.adoc | |
| parent | 6053cf02252c8f6e9f58ccc366b1e0d0a3eb02d4 (diff) | |
| download | riscv-isa-manual-1078de3a8e6ffd01a6ea8e6f19950dc6309b4ca8.zip riscv-isa-manual-1078de3a8e6ffd01a6ea8e6f19950dc6309b4ca8.tar.gz riscv-isa-manual-1078de3a8e6ffd01a6ea8e6f19950dc6309b4ca8.tar.bz2 | |
Added a missing closing bracket.
Added a missing closing bracket.
Diffstat (limited to 'src/intro.adoc')
| -rw-r--r-- | src/intro.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index 5878465..87c7701 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -413,7 +413,7 @@ and avoid reading main memory for instruction fetches ever again. To ensure that certain implicit reads are ordered only after writes to the same memory locations, software must execute specific fence or cache-control instructions defined for this purpose (such as the FENCE.I -instruction defined in <<zifencei, Chapter 3>>. +instruction defined in <<zifencei, Chapter 3>>). (((memory access, implicit and explicit))) The memory accesses (implicit or explicit) made by a hart may appear to |