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| author | Bill Traynor <wmat@riscv.org> | 2022-12-15 12:24:19 -0800 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-12-15 12:24:19 -0800 |
| commit | e394dd0295b2f75da37fb4eec81c567a1ee98c08 (patch) | |
| tree | 5121d4f9181180680624e1406d08b0533a0b9fb4 /src/intro.adoc | |
| parent | 357f654bf034b6b0c5480d08c6132bd506bece82 (diff) | |
| download | riscv-isa-manual-e394dd0295b2f75da37fb4eec81c567a1ee98c08.zip riscv-isa-manual-e394dd0295b2f75da37fb4eec81c567a1ee98c08.tar.gz riscv-isa-manual-e394dd0295b2f75da37fb4eec81c567a1ee98c08.tar.bz2 | |
Fixed spacing issue.
Fixed spacing issue between paragraphs after Tip.
Diffstat (limited to 'src/intro.adoc')
| -rw-r--r-- | src/intro.adoc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index 4fb5b12..a791ca6 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -570,7 +570,6 @@ such an instruction borders a protection boundary, complicating variable-instruction-length fetch and decode. ==== (((endian, little and big))) - RISC-V base ISAs have either little-endian or big-endian memory systems, with the privileged architecture further defining bi-endian operation. Instructions are stored in memory as a sequence of 16-bit little-endian |