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| author | Bill Traynor <wmat@riscv.org> | 2023-01-31 16:48:11 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-01-31 16:48:11 -0500 |
| commit | ce2c026be14337af36fde7aaf025290df24bd2e5 (patch) | |
| tree | 37f006db4a5599d176818228103b590dfa7d0b3a /src/images/wavedrom | |
| parent | 5e1701a31814d871d25fe113fbb439128ed70a5a (diff) | |
| download | riscv-isa-manual-ce2c026be14337af36fde7aaf025290df24bd2e5.zip riscv-isa-manual-ce2c026be14337af36fde7aaf025290df24bd2e5.tar.gz riscv-isa-manual-ce2c026be14337af36fde7aaf025290df24bd2e5.tar.bz2 | |
Testing multi line wavedrom
Testing multiline wavedrom
Diffstat (limited to 'src/images/wavedrom')
| -rw-r--r-- | src/images/wavedrom/test.adoc | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/images/wavedrom/test.adoc b/src/images/wavedrom/test.adoc new file mode 100644 index 0000000..4c7da84 --- /dev/null +++ b/src/images/wavedrom/test.adoc @@ -0,0 +1,59 @@ +### CR : Register +${wd({reg: [ + {bits: 2, name: 'op', type: 8}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 5, name: 'rd / rs1', type: 7}, + {bits: 4, name: 'funct4', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 5, name: 'imm', type: 3}, + {bits: 5, name: 'rd / rs1', type: 7}, + {bits: 1, name: 'imm', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 6, name: 'imm', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 3, name: 'rd`', type: 2}, + {bits: 8, name: 'imm', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 3, name: 'rd`', type: 2}, + {bits: 2, name: 'imm', type: 3}, + {bits: 3, name: 'rs1`', type: 4}, + {bits: 3, name: 'imm', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 3, name: 'rs2`', type: 4}, + {bits: 2, name: 'imm', type: 3}, + {bits: 3, name: 'rs1`', type: 4}, + {bits: 3, name: 'imm', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 3, name: 'rs2`', type: 4}, + {bits: 2, name: 'funct2', type: 8}, + {bits: 3, name: 'rd` / rs1`', type: 7}, + {bits: 6, name: 'funct6', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 5, name: 'offset', type: 3}, + {bits: 3, name: 'rd` / rs1`', type: 7}, + {bits: 3, name: 'offset', type: 3}, + {bits: 3, name: 'funct3', type: 8}, + + {bits: 2, name: 'op', type: 8}, + {bits: 11, name: 'jump target', type: 3}, + {bits: 3, name: 'funct3', type: 8}, +], config: { + hflip: true, + compact: true, + bits: 16 * 9, lanes: 9, + margin: {right: width / 4}, + label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']} +}})}
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