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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-19 20:06:32 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-19 20:06:32 -0700 |
| commit | 14f269d349d4e0f211752b3217bf7958ed6fc5d2 (patch) | |
| tree | 43593eb2ef45bfdb67bea62b82f194225642e472 /src/hypervisor.tex | |
| parent | 66ca5c0d95686839f3c7e41d7cfe7428b7dc8693 (diff) | |
| download | riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.zip riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.tar.gz riscv-isa-manual-14f269d349d4e0f211752b3217bf7958ed6fc5d2.tar.bz2 | |
Excised H-mode from spec.
Diffstat (limited to 'src/hypervisor.tex')
| -rw-r--r-- | src/hypervisor.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 03b52d2..6aaf24b 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -1,8 +1,8 @@ -\chapter{Hypervisor-Level ISA} +\chapter{Hypervisor Extensions, Version 1.0-draft} \label{hypervisor} -This chapter is a placeholder for a future RISC-V hypervisor-level -common core specification. +This chapter presents an early proposal for RISC-V hypervisor support +with an extended S-mode. \begin{commentary} The privileged architecture is designed to simplify the use of classic |