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author | Andrew Waterman <andrew@sifive.com> | 2017-12-12 18:34:19 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-12-12 18:34:19 -0800 |
commit | be904e62ede28fb14d41090c97394120ccb6cadb (patch) | |
tree | 540322bcbc0687822a855a2fe5e5b17b4fd9f840 /src/history.tex | |
parent | 272d038abebe7f006ed7960b522f1e51890bb982 (diff) | |
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-rw-r--r-- | src/history.tex | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/history.tex b/src/history.tex index 269384c..4263883 100644 --- a/src/history.tex +++ b/src/history.tex @@ -55,7 +55,9 @@ Maven ISA. Christopher Celio provided the initial definition of a traditional vector instruction set (``Flood'') variant of Maven. Based on experience with all these previous projects, the RISC-V ISA -definition was begun in Summer 2010. An initial version of the RISC-V +definition was begun in Summer 2010, with Andrew Waterman, Yunsup Lee, +Krste Asanovi\'{c}, and David Patterson as principal designers. +An initial version of the RISC-V 32-bit instruction subset was used in the UC Berkeley Fall 2010 CS250 VLSI Systems Design class, with Yunsup Lee as TA. RISC-V is a clean break from the earlier MIPS-inspired designs. John Hauser contributed @@ -195,7 +197,7 @@ Chisnall, Stefan Freudenberger, John Hauser, Ben Keller, Rishiyur Nikhil, Michael Taylor, Tommy Thorn, and Robert Watson for comments on the draft ISA version 2.0 specification. -\section{History for Revision 2.1} +\section{History from Revision 2.1} Uptake of the RISC-V ISA has been very rapid since the introduction of the frozen version 2.0 in May 2014, with too much activity to record @@ -211,7 +213,7 @@ Thanks to Scott Beamer, Allen J. Baum, Christopher Celio, David Chisnall, Paul Clayton, Palmer Dabbelt, Jan Gray, Michael Hamburg, and John Hauser for comments on the version 2.0 specification. -\section{History for Revision 2.2} +\section{History from Revision 2.2} \section*{Acknowledgments} @@ -219,6 +221,16 @@ Hauser for comments on the version 2.0 specification. Thanks to Jacob Bachmeyer, Alex Bradbury, David Horner, Stefan O'Rear, and Joseph Myers for comments on the version 2.1 specification. +\section{History for Revision 2.3} + +Uptake of RISC-V continues at breakneck pace. + +John Hauser and Andrew Waterman contributed a hypervisor ISA extension +based upon a proposal from Paolo Bonzini. + +Daniel Lustig, Arvid, and \fixme{} contributed the RISC-V memory consistency +model. + \section{Funding} Development of the RISC-V architecture and implementations has been |