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| author | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:25:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-05-30 22:26:42 -0700 |
| commit | 40cf9350a6bf1c47d21a91fcdd1ba62a28731303 (patch) | |
| tree | 14484d7243dd344af851687d7fa9cd642b19ab54 /src/history.tex | |
| parent | d01dabf2c290dae77d12c8cfa288e6f9ac95cb55 (diff) | |
| download | riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.zip riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.gz riscv-isa-manual-40cf9350a6bf1c47d21a91fcdd1ba62a28731303.tar.bz2 | |
Hyphenate "instruction set" when it's part of a noun phrase
Diffstat (limited to 'src/history.tex')
| -rw-r--r-- | src/history.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/history.tex b/src/history.tex index 8e6713d..0e6e816 100644 --- a/src/history.tex +++ b/src/history.tex @@ -104,7 +104,7 @@ disadvantages: Our position is that the ISA is perhaps the most important interface in a computing system, and there is no reason that such an important interface should be proprietary. The dominant commercial ISAs are -based on instruction set concepts that were already well known over 30 +based on instruction-set concepts that were already well known over 30 years ago. Software developers should be able to target an open standard hardware target, and commercial processor designers should compete on implementation quality. @@ -143,7 +143,7 @@ projects using RISC-V. \section{History from Revision 1.0 of ISA manual} -The RISC-V ISA and instruction set manual builds upon several earlier +The RISC-V ISA and instruction-set manual builds upon several earlier projects. Several aspects of the supervisor-level machine and the overall format of the manual date back to the T0 (Torrent-0) vector microprocessor project at UC Berkeley and ICSI, begun in 1992. T0 was |