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authorKrste Asanovic <krste@eecs.berkeley.edu>2018-01-23 18:03:35 -0800
committerKrste Asanovic <krste@eecs.berkeley.edu>2018-01-23 18:03:35 -0800
commit7bfd26660ad4249197746c8f9eef0b47c70d5637 (patch)
tree8e3087afac838dc3014e566434777f9fd43b3df6 /src/f.tex
parent7e92970c25d6c245d78875465a65133bb228a727 (diff)
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Standardized on pseudoinstruction.
Closes #122
Diffstat (limited to 'src/f.tex')
-rw-r--r--src/f.tex10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/f.tex b/src/f.tex
index f47c0ef..8a29e68 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -128,7 +128,7 @@ holds the accrued exception flags, as shown in Figure~\ref{fcsr}.
\end{figure*}
The {\tt fcsr} register can be read and written with the FRCSR and
-FSCSR instructions, which are assembler pseudo-ops built on the
+FSCSR instructions, which are assembler psuedo-instructions built on the
underlying CSR access instructions. FRCSR reads {\tt fcsr} by copying
it into integer register {\em rd}. FSCSR swaps the value in {\tt
fcsr} by copying the original value into integer register {\em rd},
@@ -136,7 +136,7 @@ and then writing a new value obtained from integer register {\em rs1}
into {\tt fcsr}.
The fields within the {\tt fcsr} can also be accessed individually
-through different CSR addresses, and separate assembler pseudo-ops are
+through different CSR addresses, and separate assembler psuedo-instructions are
defined for these accesses. The FRRM instruction reads the Rounding
Mode field {\tt frm} and copies it into the least-significant three
bits of integer register {\em rd}, with zero in all other bits. FSRM
@@ -560,11 +560,11 @@ of {\em rs2}'s sign bit; and for FSGNJX, the sign bit is the XOR of
the sign bits of {\em rs1} and {\em rs2}. Sign-injection instructions
do not set floating-point exception flags, nor do they canonicalize
NaNs. Note, FSGNJ.S {\em rx, ry,
- ry} moves {\em ry} to {\em rx} (assembler pseudo-op FMV.S {\em rx,
+ ry} moves {\em ry} to {\em rx} (assembler psuedo-instruction FMV.S {\em rx,
ry}); FSGNJN.S {\em rx, ry, ry} moves the negation of {\em ry} to
-{\em rx} (assembler pseudo-op FNEG.S {\em rx, ry}); and FSGNJX.S {\em rx,
+{\em rx} (assembler psuedo-instruction FNEG.S {\em rx, ry}); and FSGNJX.S {\em rx,
ry, ry} moves the absolute value of {\em ry} to {\em rx} (assembler
-pseudo-op FABS.S {\em rx, ry}).
+psuedo-instruction FABS.S {\em rx, ry}).
\vspace{-0.2in}
\begin{center}