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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-02 18:53:23 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-02 19:03:09 -0800 |
| commit | 5c5fa59c65454a66f7afbf1ca789fab3997e2ef2 (patch) | |
| tree | 6cc323d186ad9782e2888069028de2362aa4502e /src/f.tex | |
| parent | 6b822b68962fb190bfb6d1ab7695284e74c1ba65 (diff) | |
| download | riscv-isa-manual-5c5fa59c65454a66f7afbf1ca789fab3997e2ef2.zip riscv-isa-manual-5c5fa59c65454a66f7afbf1ca789fab3997e2ef2.tar.gz riscv-isa-manual-5c5fa59c65454a66f7afbf1ca789fab3997e2ef2.tar.bz2 | |
Clarify behavior of FCSR MSBs
Diffstat (limited to 'src/f.tex')
| -rw-r--r-- | src/f.tex | 8 |
1 files changed, 7 insertions, 1 deletions
@@ -106,7 +106,7 @@ holds the accrued exception flags, as shown in Figure~\ref{fcsr}. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{0} & +\multicolumn{1}{|c|}{{\em Reserved}} & \multicolumn{1}{c|}{Rounding Mode ({\tt frm})} & \multicolumn{5}{c|}{Accrued Exceptions ({\tt fflags})} \\ \hline @@ -148,6 +148,12 @@ Accrued Exception Flags field {\tt fflags}. Additional pseudo-instructions FSRMI and FSFLAGSI swap values using an immediate value instead of register {\em rs1}. +Bits 31--8 of the {\tt fcsr} are reserved for other standard extensions, +including the ``L'' standard extension for decimal floating-point. If +these extensions are not present, implementations shall ignore writes to +these bits and supply a zero value when read. Standard software should +preserve the contents of these bits. + Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in {\tt frm}. Rounding modes are encoded as shown in Table~\ref{rm}. A value of 111 in the instruction's {\em |