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| author | Philipp Wagner <phw@lowrisc.org> | 2020-03-23 22:01:04 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-23 15:01:04 -0700 |
| commit | 5f5b33e03def490645e7ffd7705b235ed0f98634 (patch) | |
| tree | 4e533a34524e0c0b61b8fbc207b928a591d85d79 /src/extensions.tex | |
| parent | e21e963f607cc8beb64c2182adfcc1cfadac9ede (diff) | |
| download | riscv-isa-manual-5f5b33e03def490645e7ffd7705b235ed0f98634.zip riscv-isa-manual-5f5b33e03def490645e7ffd7705b235ed0f98634.tar.gz riscv-isa-manual-5f5b33e03def490645e7ffd7705b235ed0f98634.tar.bz2 | |
Extensions: List all integer base ISAs (#493)
The text currently mandates extensions to build on top of any base
integer ISA, but only lists two of them (RV32I and RV64I). Add the two
remaining ones (RV32E and RV128I) as well.
Diffstat (limited to 'src/extensions.tex')
| -rw-r--r-- | src/extensions.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/extensions.tex b/src/extensions.tex index 6eaf116..5daa377 100644 --- a/src/extensions.tex +++ b/src/extensions.tex @@ -26,9 +26,9 @@ extensions. \subsection*{Standard versus Non-Standard Extension} Any RISC-V processor implementation must support a base integer ISA -(RV32I or RV64I). In addition, an implementation may support one or -more extensions. We divide extensions into two broad categories: {\em - standard} versus {\em non-standard}. +(RV32I, RV32E, RV64I, or RV128I). In addition, an implementation may +support one or more extensions. We divide extensions into two broad +categories: {\em standard} versus {\em non-standard}. \begin{itemize} \item A standard extension is one that is generally useful and that is designed to not conflict with any other standard extension. |