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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 17:08:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 17:08:03 -0700 |
| commit | 70ff7c2cb5ae63ea230a362f2a9f04795ffe30f1 (patch) | |
| tree | 6f975b4c111993e7153be0662b111a9e0ae95a51 /src/extensions.tex | |
| parent | 1e8c2e1fc2c1fd4a5b9177869aee8ace4b5879bb (diff) | |
| download | riscv-isa-manual-70ff7c2cb5ae63ea230a362f2a9f04795ffe30f1.zip riscv-isa-manual-70ff7c2cb5ae63ea230a362f2a9f04795ffe30f1.tar.gz riscv-isa-manual-70ff7c2cb5ae63ea230a362f2a9f04795ffe30f1.tar.bz2 | |
Changes to unprivileged spec for bi[g]-endian support
Diffstat (limited to 'src/extensions.tex')
| -rw-r--r-- | src/extensions.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/extensions.tex b/src/extensions.tex index 2517165..6eaf116 100644 --- a/src/extensions.tex +++ b/src/extensions.tex @@ -53,7 +53,8 @@ example, the base ISA is defined within a 30-bit encoding space (bits fits within a 25-bit encoding space (bits 31--7). We use the term {\em prefix} to refer to the bits to the {\em right} -of an instruction encoding space (since RISC-V is little-endian, the +of an instruction encoding space (since instruction fetch in RISC-V is +little-endian, the bits to the right are stored at earlier memory addresses, hence form a prefix in instruction-fetch order). The prefix for the standard base ISA encoding is the two-bit ``11'' field held in bits 1--0 of the |