Formatting fixes

1 files changed, 5 insertions, 5 deletions

diff --git a/src/d.tex b/src/d.tex
index 3b29b1f..942e350 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -26,18 +26,18 @@ extension is supported.
 \label{nanboxing}
 
 When multiple floating-point precisions are supported, then valid
-values of narrower $n$-bit types, $n<$FLEN, are represented in the
+values of narrower $n$-bit types, \mbox{$n<$ FLEN}, are represented in the
 lower $n$ bits of an FLEN-bit NaN value, in a process termed
 NaN-boxing.  The upper bits of a valid NaN-boxed value must be all 1s.
 Valid NaN-boxed $n$-bit values therefore appear as negative quiet NaNs
-(qNaNs) when viewed as any wider $m$-bit value, $n < m \leq$FLEN.
+(qNaNs) when viewed as any wider $m$-bit value, \mbox{$n < m \leq$ FLEN}.
 
 \begin{commentary}
 Software might not know the current type of data stored in a
 floating-point register but has to be able to save and restore the
 register values, hence the result of using wider operations to
 transfer narrower values has to be defined.  A common case is for
-callee-save registers, but a standard convention is also desirable for
+callee-saved registers, but a standard convention is also desirable for
 features including varargs, user-level threading libraries, virtual
 machine migration, and debugging.
 \end{commentary}
@@ -46,7 +46,7 @@ Floating-point $n$-bit transfer operations move external values held
 in IEEE standard formats into and out of the {\tt f} registers, and
 comprise floating-point loads and stores (FL$n$/FS$n$) and
 floating-point move instructions (FMV.$n$.X/FMV.X.$n$).  A narrower
-$n$-bit transfer, $n<$FLEN, into the {\tt f} registers will create a
+$n$-bit transfer, \mbox{$n<$ FLEN}, into the {\tt f} registers will create a
 valid NaN-boxed value by setting all upper FLEN$-n$ bits of the
 destination {\tt f} register to 1.  A narrower $n$-bit transfer out of
 the floating-point registers will transfer the lower $n$ bits of the
@@ -54,7 +54,7 @@ register ignoring the upper FLEN$-n$ bits.
 
 Floating-point compute and sign-injection operations calculate results
 based on the FLEN-bit values held in the {\tt f} registers.  A narrow
-$n$-bit operation, where $n<$FLEN, checks that input operands are
+$n$-bit operation, where \mbox{$n<$ FLEN}, checks that input operands are
 correctly NaN-boxed, i.e., all upper FLEN$-n$ bits are 1.  If so, the
 $n$ least-significant bits of the input are used as the input value,
 otherwise the input value is treated as an $n$-bit canonical NaN.  An