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author | Daniel Lustig <dlustig@nvidia.com> | 2018-07-05 15:53:28 -0700 |
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committer | Daniel Lustig <dlustig@nvidia.com> | 2018-07-05 15:59:25 -0700 |
commit | b170645fa6f8143b5927cccb27a740064589ba35 (patch) | |
tree | b90c8bf73f97a61f515a4a7774b0b7bdd6da5dec /src/d.tex | |
parent | 4efa37665abe4198ff46fdf2c5cbf42a385a0427 (diff) | |
download | riscv-isa-manual-b170645fa6f8143b5927cccb27a740064589ba35.zip riscv-isa-manual-b170645fa6f8143b5927cccb27a740064589ba35.tar.gz riscv-isa-manual-b170645fa6f8143b5927cccb27a740064589ba35.tar.bz2 |
FLD and FST are not atomic unless XLEN>=64
Diffstat (limited to 'src/d.tex')
-rw-r--r-- | src/d.tex | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -94,6 +94,7 @@ allowing the datapath muxing to be shared. \end{commentary} \section{Double-Precision Load and Store Instructions} +\label{fld_fst} The FLD instruction loads a double-precision floating-point value from memory into floating-point register {\em rd}. FSD stores a double-precision |