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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-07 23:46:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-07 23:46:35 -0700 |
| commit | 3536b679c4fcfb2cf833302d1bf960864b4c4a66 (patch) | |
| tree | 0c276ceca5fb9f540ced27cdc63601e43735721d /src/d.tex | |
| parent | ce5e74a66ea22327702eca09e7a868db7e9615e9 (diff) | |
| download | riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.zip riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.tar.gz riscv-isa-manual-3536b679c4fcfb2cf833302d1bf960864b4c4a66.tar.bz2 | |
Use \geq instead of >=
Diffstat (limited to 'src/d.tex')
| -rw-r--r-- | src/d.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -317,7 +317,7 @@ FSGNJ & D & src2 & src1 & J[N]/JX & dest & OP-FP \\ \end{tabular} \end{center} -For XLEN$>=$64 only, instructions are provided to move bit patterns +For XLEN$\geq$64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register {\em rs1} to a representation in IEEE 754-2008 standard encoding in integer register |