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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-30 19:06:47 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-30 19:06:47 -0800 |
| commit | 8000427d76509bd68ae0333dbc383667736edd20 (patch) | |
| tree | 03d52935bb733dc1fa63c9d9220b06d74e254a4e /src/d-st-ext.adoc | |
| parent | 3e395b42d5786450a4237e1ecffb4711b2d30b1e (diff) | |
| download | riscv-isa-manual-8000427d76509bd68ae0333dbc383667736edd20.zip riscv-isa-manual-8000427d76509bd68ae0333dbc383667736edd20.tar.gz riscv-isa-manual-8000427d76509bd68ae0333dbc383667736edd20.tar.bz2 | |
Fix >= formatting errors
Diffstat (limited to 'src/d-st-ext.adoc')
| -rw-r--r-- | src/d-st-ext.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc index b95076c..4274017 100644 --- a/src/d-st-ext.adoc +++ b/src/d-st-ext.adoc @@ -108,7 +108,7 @@ include::images/wavedrom/double-ls.adoc[] //.Double-precision load and store FLD and FSD are only guaranteed to execute atomically if the effective -address is naturally aligned and XLENlatexmath:[$\geq$]64. +address is naturally aligned and XLEN≥64. FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. @@ -169,7 +169,7 @@ sign-injection instruction. include::images/wavedrom/fsjgnjnx-d.adoc[] //.Double-precision sign-injection -For XLENlatexmath:[$\geq$]64 only, instructions are provided to move bit +For XLEN≥64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register _rs1_ to a representation in IEEE 754-2008 standard encoding in integer register |