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author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 14:46:17 -0800 |
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committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-11-06 14:46:17 -0800 |
commit | efa2a40a2329717142cb975d93c7b3f6ab473295 (patch) | |
tree | f6eec9adac87335e7f4ae819bcd1c293d6cdc890 /src/csr.tex | |
parent | 25358c650b145cf9951601d197856cb5a84ec86e (diff) | |
download | riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.zip riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.tar.gz riscv-isa-manual-efa2a40a2329717142cb975d93c7b3f6ab473295.tar.bz2 |
Gave CSR instruction module a name and a version, and made clear these are being ratified also.
Diffstat (limited to 'src/csr.tex')
-rw-r--r-- | src/csr.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/csr.tex b/src/csr.tex index 932b450..8c1b923 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -1,4 +1,4 @@ -\chapter{Control and Status Register (CSR) Instructions} +\chapter{``Zicsr'', Control and Status Register (CSR) Instructions, Version 2.0} \label{csrinsts} RISC-V defines a separate address space of 4096 Control and Status |