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| author | wmat <wmat@riscv.org> | 2024-04-09 15:34:25 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-04-09 15:34:25 -0400 |
| commit | d125ebd61769cefce9f4327aa839a65018a84975 (patch) | |
| tree | 811b601a95a07578ca5791dd366b8a359be29ae4 /src/counters.adoc | |
| parent | c6cf0cb45b539fa27309ef1cfca19a568e98735d (diff) | |
| download | riscv-isa-manual-d125ebd61769cefce9f4327aa839a65018a84975.zip riscv-isa-manual-d125ebd61769cefce9f4327aa839a65018a84975.tar.gz riscv-isa-manual-d125ebd61769cefce9f4327aa839a65018a84975.tar.bz2 | |
Updating chapter titles to make them consisten.
Removed extraneous use of the word Standard.
Quoted extension names when applicable.
Diffstat (limited to 'src/counters.adoc')
| -rw-r--r-- | src/counters.adoc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/counters.adoc b/src/counters.adoc index cf646c6..f4a34af 100644 --- a/src/counters.adoc +++ b/src/counters.adoc @@ -1,5 +1,5 @@ [[counters]] -== "Zicntr" and "Zihpm" Counters, Version 2.0 +== "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0 RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are accessible via unprivileged XLEN-bit @@ -7,7 +7,7 @@ read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits are accessed via CSR registers `0xC80`–`0xC9F`). These counters are divided between the "Zicntr" and "Zihpm" extensions. -=== "Zicntr" Standard Extension for Base Counters and Timers +=== "Zicntr" Extension for Base Counters and Timers The Zicntr standard extension comprises the first three of these counters (CYCLE, TIME, and INSTRET), which have dedicated functions @@ -173,7 +173,7 @@ reading its upper and lower halves. bne x3, x4, again -=== "Zihpm" Standard Extension for Hardware Performance Counters +=== "Zihpm" Extension for Hardware Performance Counters The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, `hpmcounter3-hpmcounter31`. When |