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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-04-24 02:16:21 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-04-24 02:16:21 -0700 |
| commit | 48adfafd1136f5d01936426c621b0c25d7cc9021 (patch) | |
| tree | c3ef5a4475d19ee76a362976e863cfa0a5401425 /src/assembly.tex | |
| parent | 3393682b4d0d6a0d1e2244ff8e909c4dcb5511cb (diff) | |
| download | riscv-isa-manual-48adfafd1136f5d01936426c621b0c25d7cc9021.zip riscv-isa-manual-48adfafd1136f5d01936426c621b0c25d7cc9021.tar.gz riscv-isa-manual-48adfafd1136f5d01936426c621b0c25d7cc9021.tar.bz2 | |
Modified behavior of JALR hint bits to better support macro-op fusion of LUI;JALR pair.
Diffstat (limited to 'src/assembly.tex')
| -rw-r--r-- | src/assembly.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/assembly.tex b/src/assembly.tex index de2d2e5..d58f33d 100644 --- a/src/assembly.tex +++ b/src/assembly.tex @@ -18,7 +18,8 @@ registers and their role in the standard calling convention. \tt x2 & \tt sp & Stack pointer & Callee \\ \tt x3 & \tt gp & Global pointer & --- \\ \tt x4 & \tt tp & Thread pointer & --- \\ - {\tt x5}--{\tt 7} & {\tt t0}--{\tt 2} & Temporaries & Caller \\ + \tt x5 & {\tt t0} & Temporary/alternate link register& Caller \\ + {\tt x6}--{\tt 7} & {\tt t1}--{\tt 2} & Temporaries & Caller \\ \tt x8 & {\tt s0}/\tt fp & Saved register/frame pointer & Callee \\ \tt x9 & {\tt s1} & Saved register & Callee \\ {\tt x10}--{\tt 11} & {\tt a0}--{\tt 1} & Function arguments/return values & Caller \\ |