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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-08 14:41:24 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-08 14:41:31 -0800 |
| commit | 2c07340049ea7f91013b84bb1a8d798fb3e2d8d2 (patch) | |
| tree | 447e2eb93a2852009e039111bc5c6e251a816ccf /src/a.tex | |
| parent | 5890a1a702abf4157d5879717a39d8ecdae0de68 (diff) | |
| download | riscv-isa-manual-2c07340049ea7f91013b84bb1a8d798fb3e2d8d2.zip riscv-isa-manual-2c07340049ea7f91013b84bb1a8d798fb3e2d8d2.tar.gz riscv-isa-manual-2c07340049ea7f91013b84bb1a8d798fb3e2d8d2.tar.bz2 | |
LR/SC extension commentary tweak
Diffstat (limited to 'src/a.tex')
| -rw-r--r-- | src/a.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -103,7 +103,7 @@ For RV64, LR.W and SC.W sign-extend the value placed in {\em rd}. Both compare-and-swap (CAS) and LR/SC can be used to build lock-free data structures. After extensive discussion, we opted for LR/SC for several reasons: 1) CAS suffers from the ABA problem, which LR/SC -avoids because it monitors all accesses to the address rather than +avoids because it monitors all writes to the address rather than only checking for changes in the data value; 2) CAS would also require a new integer instruction format to support three source operands (address, compare value, swap value) as well as a different memory |