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authorKrste Asanovic <krste@eecs.berkeley.edu>2017-04-02 16:38:45 -0700
committerKrste Asanovic <krste@eecs.berkeley.edu>2017-04-02 16:38:45 -0700
commit659c38f572e836e54187a4032a233da9a87788e1 (patch)
tree6808c9c988ca33bce694e5d674a508c016ab5e0b /src/a.tex
parent878d4d3fde24aea2958cebe08894bf4e4a2e04d0 (diff)
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Improved rationale for AMO selection.
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@@ -319,6 +319,12 @@ microarchitecture can implement AMOs using the LR/SC primitives. More
complex implementations might also implement AMOs at memory
controllers, and can optimize away fetching the original value when
the destination is {\tt x0}.
+
+The set of AMOs was chosen to support the C11/C+11 atomic memory
+operations efficiently, and also to support parallel reductions in
+memory. Another use of AMOs is to provide atomic updates to
+memory-mapped device registers (e..g, setting, clearing, or toggling
+bits) in the I/O space.
\end{commentary}
To help implement multiprocessor synchronization, the AMOs optionally