adoc formatting and table fixes for intro, a, c, counters, m, rvmo chapters

1 files changed, 11 insertions, 10 deletions

diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index 7468009..34cdb2c 100644
--- a/src/a-st-ext.adoc
+++ b/src/a-st-ext.adoc
@@ -1,7 +1,7 @@
 [[atomics]]
-== `A` Standard Extension for Atomic Instructions, Version 2.1
+== A Standard Extension for Atomic Instructions, Version 2.1
 
-The standard atomic-instruction extension, named `A`, contains
+The standard atomic-instruction extension, named A, contains
 instructions that atomically read-modify-write memory to support
 synchronization between multiple RISC-V harts running in the same memory
 space. The two forms of atomic instruction provided are
@@ -111,7 +111,7 @@ software should only assume the failure code will be non-zero.
 
 [NOTE]
 ====
-We reserve a failure code of 1 to mean `unspecified` so that simple
+We reserve a failure code of 1 to mean *unspecified* so that simple
 implementations may return this value using the existing mux required
 for the SLT/SLTU instructions. More specific failure codes might be
 defined in future versions or extensions to the ISA.
@@ -223,6 +223,7 @@ instruction unless the _rl_ bit is also set. LR._rl_ and SC._aq_
 instructions are not guaranteed to provide any stronger ordering than
 those with both bits clear, but may result in lower performance.
 
+.Sample code for compare-and-swap function using LR/SC.
 ....
         # a0 holds address of memory location 
         # a1 holds expected value
@@ -256,10 +257,10 @@ sequence in the case of failure, and must comprise at most 16
 instructions placed sequentially in memory.
 * An LR/SC sequence begins with an LR instruction and ends with an SC
 instruction. The dynamic code executed between the LR and SC
-instructions can only contain instructions from the base `I`
+instructions can only contain instructions from the base _I_
 instruction set, excluding loads, stores, backward jumps, taken backward
-branches, JALR, FENCE, and SYSTEM instructions. If the `C` extension
-is supported, then compressed forms of the aforementioned `I`
+branches, JALR, FENCE, and SYSTEM instructions. If the _C_ extension
+is supported, then compressed forms of the aforementioned _I_
 instructions are also permitted.
 * The code to retry a failing LR/SC sequence can contain backwards jumps
 and/or branches to repeat the LR/SC sequence, but otherwise has the same
@@ -371,7 +372,7 @@ is not naturally aligned, an address-misaligned exception or an
 access-fault exception will be generated. The access-fault exception can
 be generated for a memory access that would otherwise be able to
 complete except for the misalignment, if the misaligned access should
-not be emulated. The ``Zam`` extension, described in
+not be emulated. The _Zam_ extension, described in
 <<zam>>, relaxes this requirement and specifies the
 semantics of misaligned AMOs.
 
@@ -379,7 +380,7 @@ The operations supported are swap, integer add, bitwise AND, bitwise OR,
 bitwise XOR, and signed and unsigned integer maximum and minimum.
 Without ordering constraints, these AMOs can be used to implement
 parallel reduction operations, where typically the return value would be
-discarded by writing to `x0`.
+discarded by writing to _x0_.
 
 [NOTE]
 ====
@@ -388,7 +389,7 @@ parallel systems better than LR/SC or CAS. A simple microarchitecture
 can implement AMOs using the LR/SC primitives, provided the
 implementation can guarantee the AMO eventually completes. More complex
 implementations might also implement AMOs at memory controllers, and can
-optimize away fetching the original value when the destination is `x0`.
+optimize away fetching the original value when the destination is *x0*.
 
 The set of AMOs was chosen to support the C11/C++11 atomic memory
 operations efficiently, and also to support parallel reductions in
@@ -444,7 +445,7 @@ acquire and release to simplify the implementation of speculative lock
 elision cite:[Rajwar:2001:SLE].
 ====
 
-The instructions in the `A` extension can also be used to provide
+The instructions in the _A_ extension can also be used to provide
 sequentially consistent loads and stores. A sequentially consistent load
 can be implemented as an LR with both _aq_ and _rl_ set. A sequentially
 consistent store can be implemented as an AMOSWAP that writes the old