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| author | Bill Traynor <wmat@riscv.org> | 2023-01-31 11:25:01 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-01-31 11:25:01 -0500 |
| commit | 71f0354ca3266d31d636655655aee993560c2917 (patch) | |
| tree | 0d28be2df9413ad3ee40aed8fb659b2eab18445d /src/a-st-ext.adoc | |
| parent | fa5f25481af2bf5b99a3511a5f6eff89d35c2a70 (diff) | |
| download | riscv-isa-manual-71f0354ca3266d31d636655655aee993560c2917.zip riscv-isa-manual-71f0354ca3266d31d636655655aee993560c2917.tar.gz riscv-isa-manual-71f0354ca3266d31d636655655aee993560c2917.tar.bz2 | |
Fixed code sample.
Added page break before code sample.
Added label to code sample.
Diffstat (limited to 'src/a-st-ext.adoc')
| -rw-r--r-- | src/a-st-ext.adoc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc index a142b89..7cb5d73 100644 --- a/src/a-st-ext.adoc +++ b/src/a-st-ext.adoc @@ -213,7 +213,7 @@ instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance. <<< - + [[cas]] [source,asm] .Sample code for compare-and-swap function using LR/SC. @@ -409,8 +409,11 @@ order the lock acquisition before the critical section, and the second AMO is marked _rl_ to order the critical section before the lock relinquishment. +<<< + [[critical]] [source,asm] +.Sample code for mutual exclusion. `a0` contains the address of the lock. li t0, 1 # Initialize swap value. again: lw t1, (a0) # Check if lock is held. |