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author | Andrew Waterman <andrew@sifive.com> | 2023-01-30 18:26:10 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-01-30 18:26:10 -0800 |
commit | 02c0179dfca1f08f39a8079281a0ca3b0610a083 (patch) | |
tree | aac18e8404c6c1e8b318e5dd9533fad27185444f /src/a-st-ext.adoc | |
parent | 2c9d5455ec6cb8730b35239a626c3708788be690 (diff) | |
download | riscv-isa-manual-02c0179dfca1f08f39a8079281a0ca3b0610a083.zip riscv-isa-manual-02c0179dfca1f08f39a8079281a0ca3b0610a083.tar.gz riscv-isa-manual-02c0179dfca1f08f39a8079281a0ca3b0610a083.tar.bz2 |
Fix typos
Diffstat (limited to 'src/a-st-ext.adoc')
-rw-r--r-- | src/a-st-ext.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc index deaab1e..7c88cb3 100644 --- a/src/a-st-ext.adoc +++ b/src/a-st-ext.adoc @@ -363,7 +363,7 @@ The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs can be used to implement parallel reduction operations, where typically the return value would be -discarded by writing to 'x0'. +discarded by writing to `x0`. [NOTE] ==== @@ -372,7 +372,7 @@ parallel systems better than LR/SC or CAS. A simple microarchitecture can implement AMOs using the LR/SC primitives, provided the implementation can guarantee the AMO eventually completes. More complex implementations might also implement AMOs at memory controllers, and can -optimize away fetching the original value when the destination is 'x0'. +optimize away fetching the original value when the destination is `x0`. The set of AMOs was chosen to support the C11/C++11 atomic memory operations efficiently, and also to support parallel reductions in |