integrate Zaamo and Zalrsc text (#1304)

1 files changed, 15 insertions, 6 deletions

diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index ad6652b..ff6e3f3 100644
--- a/src/a-st-ext.adoc
+++ b/src/a-st-ext.adoc
@@ -1,7 +1,7 @@
 [[atomics]]
 == "A" Extension for Atomic Instructions, Version 2.1
 
-The standard atomic-instruction extension, named "A", contains
+The atomic-instruction extension, named "A", contains
 instructions that atomically read-modify-write memory to support
 synchronization between multiple RISC-V harts running in the same memory
 space. The two forms of atomic instruction provided are
@@ -18,6 +18,10 @@ appear to have finally settled on release consistency as the standard
 memory consistency model and so the RISC-V atomic support is built
 around this model.
 ====
+
+The A extension comprises instructions provided by the Zaamo and Zalrsc
+extensions.
+
 === Specifying Ordering of Atomic Instructions
 
 The base RISC-V ISA has a relaxed memory model, with the FENCE
@@ -48,7 +52,7 @@ after any later memory operations in the same RISC-V hart and to the
 same address domain.
 
 [[sec:lrsc]]
-=== Load-Reserved/Store-Conditional Instructions
+=== "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
 
 include::images/wavedrom/load-reserve-st-conditional.adoc[]
 
@@ -114,7 +118,7 @@ for the SLT/SLTU instructions. More specific failure codes might be
 defined in future versions or extensions to the ISA.
 ====
 
-For LR and SC, the A extension requires that the address held in _rs1_
+For LR and SC, the Zalrsc extension requires that the address held in _rs1_
 be naturally aligned to the size of the operand (i.e., eight-byte
 aligned for _doublewords_ and four-byte aligned for _words_). If the
 address is not naturally aligned, an address-misaligned exception or an
@@ -250,7 +254,7 @@ using LR/SC to implement a compare-and-swap function is shown in
 [[sec:lrscseq]]
 === Eventual Success of Store-Conditional Instructions
 
-The standard A extension defines _constrained LR/SC loops_, which have
+The Zalrsc extension defines _constrained LR/SC loops_, which have
 the following properties:
 
 * The loop comprises only an LR/SC sequence and code to retry the
@@ -349,7 +353,7 @@ substantially easier to provide in some microarchitectural styles.
 ====
 
 [[sec:amo]]
-=== Atomic Memory Operations
+=== "Zaamo" Extension for Atomic Memory Operations
 
 include::images/wavedrom/atomic-mem.adoc[]
 
@@ -363,7 +367,7 @@ can either operate on _doublewords_ (RV64 only) or _words_ in memory. For
 RV64, 32-bit AMOs always sign-extend the value placed in _rd_, and
 ignore the upper 32 bits of the original value of _rs2_.
 
-For AMOs, the A extension requires that the address held in _rs1_ be
+For AMOs, the Zaamo extension requires that the address held in _rs1_ be
 naturally aligned to the size of the operand (i.e., eight-byte aligned
 for _doublewords_ and four-byte aligned for _words_). If the address
 is not naturally aligned, an address-misaligned exception or an
@@ -404,6 +408,11 @@ operations efficiently, and also to support parallel reductions in
 memory. Another use of AMOs is to provide atomic updates to
 memory-mapped device registers (e.g., setting, clearing, or toggling
 bits) in the I/O space.
+
+The Zaamo extension enables microcontroller class implementations to utilize
+atomic primitives from the AMO subset of the A extension. Typically such
+implementations do not have caches and thus may not be able to naturally support
+the LR/SC instructions provided by the Zalrsc extension.
 ====
 
 To help implement multiprocessor synchronization, the AMOs optionally